Senior CAD Engineer - AI/TPU Hardware Design

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google LLC in Sunnyvale, CA is seeking a Senior Hardware Engineer to shape TPU design and verification for AI/ML acceleration. You will lead CAD methodology and collaborate across chip teams to deliver robust RTL and DV tooling for cutting-edge silicon.

The role emphasizes leadership in a fluid team environment, driving tool flow improvements and multi-area collaboration to enable first-time-right designs in TPUs and related AI hardware. English communication and cross-team impact are key.

Qualifications

• Requires a Bachelor’s degree in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
• At least 5 years experience with CAD and hardware design tools.
• Experience with SystemVerilog, hardware design, automation, and design verification testing.
• Experience developing tools in Python or C/C++.

Responsibilities

• Lead CAD methodology engineers to support chip RTL and DV teams.
• Collaborate with chip project teams to standardize methodology across areas and regions.
• Evaluate tools for potential deployment and use within flows.
• Work with Google teams to identify opportunities for improving chip design.
• Participate in design reviews and track issue resolution with trade-off discussions.

Skills

CAD

SystemVerilog

Hardware design

Automation

Design verification

Python

C/C++

Education

Bachelor's degree in Electrical Engineering, Computer Science Engineering, or equivalent

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or related field

Job description

Google LLC in Sunnyvale, CA is seeking a Senior Hardware Engineer to shape TPU design and verification for AI/ML acceleration. You will lead CAD methodology and collaborate across chip teams to deliver robust RTL and DV tooling for cutting-edge silicon.

The role emphasizes leadership in a fluid team environment, driving tool flow improvements and multi-area collaboration to enable first-time-right designs in TPUs and related AI hardware. English communication and cross-team impact are key.