TPU PCIe Design Lead

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Inc. Sunnyvale is seeking an experienced PCIe Design Engineer to shape the future of AI/ML hardware acceleration, focusing on TPU architecture and integration.

You will design and verify SoC-level RTL for next-gen data center accelerators, building clocking, reset, error handling, and power management.

Join a collaborative team advancing Google's TPUs, driving silicon bring-up and performance for AI infrastructure.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience.
• 10 years of ASIC design experience, including a PCIe project.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog RTL development and microarchitecture definition.
• Experience with PCIe protocol layers or LTSSM.
• Knowledge of CDC, timing closure, or synthesis flows.

Responsibilities

• Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs meet PPA targets and coding standards.
• Manage the full RTL lifecycle, including documentation and sign-off for Lint, CDC, and synthesis.
• Partner with system architects to meet chip-level bandwidth, latency, and power goals.
• Coordinate with Verification and Physical Design teams to develop test plans, PCIe VIP usage, and timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up for link integrity.

Skills

ASIC design

PCIe protocol expertise

RTL debugging with Verdi/VCS

Python/Perl scripting

SystemVerilog/Verilog RTL

CDC and timing closure

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD preferred

Tools

Verdi

VCS

PCIe VIP

Python/Perl scripting

Job description

corporate_fare Google place Sunnyvale, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic.
• Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.
• Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
• Experience in PCIe architecture, including Link Training and Status State Machine (LTSSM), TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
• Knowledge of ASIC flow, SerDes, and scripting.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering AI and machine learning workloads in data centers.

As a Peripheral Component Interconnect Express (PCIe) Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. You will build the foundational SoC infrastructure, including clocking, reset, error handling, and chip management that powers silicon beyond designing high-performance PCIe subsystems.

This position offers the opportunity to work on challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google .

• Lead the PCIe microarchitecture and Register-Transfer Level (RTL) development, ensuring high-performance designs that strictly adhere to Power, Performance, and Area (PPA) targets, coding standards, and quality guidelines.
• Manage the full RTL life-cycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.
• Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
• Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.