TPU SoC Architect — RTL Design for AI Acceleration

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is shaping the future of AI/ML hardware acceleration. As a Soc Design Engineer on the TPU team, you’ll contribute RTL design for data center accelerators, implement global bus architectures, and collaborate with ASIC teams to meet timing, power, and manufacturability goals.

You’ll own microarchitecture definitions, write high-quality SystemVerilog RTL, and partner with Verification and Physical Design to ensure correctness and efficiency in a highly cross-functional environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with emphasis on computer architecture.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high-quality, power-efficient RTL code, primarily in SystemVerilog.
• Partner with Verification to develop test plans, debug RTL, and ensure functional correctness.
• Work with Physical Design to meet timing, area, power, and manufacturability requirements.
• Contribute to design tools, flows, and methodologies.

Skills

Scripting languages

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Job description

Google is shaping the future of AI/ML hardware acceleration. As a Soc Design Engineer on the TPU team, you’ll contribute RTL design for data center accelerators, implement global bus architectures, and collaborate with ASIC teams to meet timing, power, and manufacturability goals.

You’ll own microarchitecture definitions, write high-quality SystemVerilog RTL, and partner with Verification and Physical Design to ensure correctness and efficiency in a highly cross-functional environment.