Senior RTL Design & TPU Architecture Engineer

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google in Sunnyvale is seeking an RTL Design Engineer to shape the future of AI/ML hardware acceleration on the TPU. You’ll own microarchitecture and RTL coding for high-performance digital designs powering TPU accelerators.

Collaborate with Verification, Physical Design, and Firmware to meet timing, power, and area goals, while driving tool development and post-silicon support. The role offers impact at scale across Google Cloud and data centers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Experience in optimizing for performance, power, and area.
• Cross-functional experience with DV and PD teams.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.
• Support post-silicon validation and hardware debugging efforts to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Skills

RTL design

Digital design

Microarchitecture design

Performance/power/area optimization

Cross-functional DV/PD collaboration

Hardware verification collaboration

RTL coding

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

Tools

PowerArtist

PTPX

Linting

CDC

RDC

LEC

Python

Perl

Job description

Google in Sunnyvale is seeking an RTL Design Engineer to shape the future of AI/ML hardware acceleration on the TPU. You’ll own microarchitecture and RTL coding for high-performance digital designs powering TPU accelerators.

Collaborate with Verification, Physical Design, and Firmware to meet timing, power, and area goals, while driving tool development and post-silicon support. The role offers impact at scale across Google Cloud and data centers.