TPU SoC Design Engineer - AI Hardware

Google; Sunnyvale (CA); On-site; USD 116,000 - 166,000; Full time

Job summary

Google is seeking an Early TPU SoC Design Engineer in Sunnyvale, CA to help shape AI/ML hardware acceleration and contribute to TPU architecture, RTL design, and verification. You will work on SoC-level RTL design, high-level integration, and cross‑functional collaboration across engineering teams.

The role offers exposure to cutting-edge ASIC development and advancement opportunities in a fast‑moving environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write performant, and power‑efficient RTL code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

Skills

ASIC RTL design

SystemVerilog/Verilog

Digital design concepts

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.

Tools

EDA tools for simulation, synthesis, power analysis

Job description

Google is seeking an Early TPU SoC Design Engineer in Sunnyvale, CA to help shape AI/ML hardware acceleration and contribute to TPU architecture, RTL design, and verification. You will work on SoC-level RTL design, high-level integration, and cross‑functional collaboration across engineering teams.

The role offers exposure to cutting-edge ASIC development and advancement opportunities in a fast‑moving environment.