TPU Hardware Design Engineer — AI Accelerators

Google; United States; On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring a TPU Design Engineer, Silicon in Mountain View, CA or San Diego, CA. You will work on custom silicon for Google's hardware products, with a focus on RTL design, power-aware implementations, and high-performance blocks.

This role requires strong digital design skills and collaborative leadership within multi-disciplinary teams. Minimum qualifications include a Bachelor's degree or equivalent, 4 years in RTL/Verilog/SystemVerilog, and experience with logic synthesis for power and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Responsibilities

• Use simulation/emulation/power analysis tools to ensure power and performance meet defined specifications.
• Develop, implement, and maintain design blocks or components/parts of a hardware product, and integrate them into subsystems.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Take a leadership role on technical project teams and set technical direction.

Skills

Digital logic design

RTL design

Verilog

SystemVerilog

Logic synthesis

Low-power design

Education

Bachelor's degree or equivalent experience

Master's or PhD (preferred)

Job description

Google is hiring a TPU Design Engineer, Silicon in Mountain View, CA or San Diego, CA. You will work on custom silicon for Google's hardware products, with a focus on RTL design, power-aware implementations, and high-performance blocks.

This role requires strong digital design skills and collaborative leadership within multi-disciplinary teams. Minimum qualifications include a Bachelor's degree or equivalent, 4 years in RTL/Verilog/SystemVerilog, and experience with logic synthesis for power and