TPU ASIC Verification Manager – AI/ML Hardware

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Cloud in Sunnyvale, CA is seeking an experienced Share ASIC Design Verification Manager to lead the functional verification of TPU designs. You will shape verification strategy, guide a team across subchip, subsystem, and full-chip levels, and collaborate with front-end design, architecture, and performance groups to ensure correctness and performance.

You will develop test plans, write diagnostic code, and build monitors and checkers, driving coverage analysis and QA for high-impact

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Responsibilities

• Lead functional verification for TPU components across subchip, subsystem, and full-chip levels.
• Develop comprehensive test plans, diagnostic code, monitors and checkers for QA.
• Partner with front-end design, architecture and performance teams to ensure architectural compliance and performance goals.

Skills

verification

SystemVerilog

UVM

people management

Education

Bachelor's degree in Electrical Engineering/Computer Science

Tools

UVM

SystemVerilog

Job description

Google Cloud in Sunnyvale, CA is seeking an experienced Share ASIC Design Verification Manager to lead the functional verification of TPU designs. You will shape verification strategy, guide a team across subchip, subsystem, and full-chip levels, and collaborate with front-end design, architecture, and performance groups to ensure correctness and performance.

You will develop test plans, write diagnostic code, and build monitors and checkers, driving coverage analysis and QA for high-impact