Senior ASIC Verification Engineer - TPU AI Hardware

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity compensation

Bonus target

Job summary

Google is building the future of AI/ML hardware acceleration through TPU engineering. This role focuses on verification of complex digital designs and TPU architecture within AI/ML systems, collaborating with design and verification engineers to ensure robust silicon solutions for Google's TPU and related platforms.

You will participate in full verification lifecycles, from planning to test execution, building constrained-random environments, and driving coverage to tape-out readiness, in an

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with design verification.
• Experience with SystemVerilog.

Responsibilities

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

SystemVerilog

UVM

CR verification

Digital verification

Formal verification

Education

Bachelor's degree

Tools

SVA

Industry tools

Job description

Google is building the future of AI/ML hardware acceleration through TPU engineering. This role focuses on verification of complex digital designs and TPU architecture within AI/ML systems, collaborating with design and verification engineers to ensure robust silicon solutions for Google's TPU and related platforms.

You will participate in full verification lifecycles, from planning to test execution, building constrained-random environments, and driving coverage to tape-out readiness, in an