ASIC Formal Verification Engineer for TPU AI Hardware

Google; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking an ASIC Formal Verification Engineer in Sunnyvale to shape AI/ML hardware acceleration. You will verify TPU architecture and its integration into AI/ML systems, contribute to project definitions, verification strategies, and silicon bring-up.

You’ll work with a team enabling data-center accelerators, implement formal verification for complex digital designs, and influence next-gen data-center technology at Google.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 4 years of formal and design verification experience.
• Experience with SystemVerilog or Verilog.
• Experience with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).

Responsibilities

• Plan the formal verification strategy for digital design blocks.
• Create properties and constraints for verification.
• Verify properties using formal verification tools and methods.
• Develop reusable formal verification components and improvements to methodologies.
• Support silicon bring-up and data-center accelerator verification.

Skills

Formal verification experience

SystemVerilog/Verilog

Verification tooling

Education

Bachelor's degree in EE/CE/CS or related, or equivalent

Master's or PhD in EE/CE/CS (preferred)

Tools

Jasper

VC Formal

Questa Formal

360-DV

Job description

Google is seeking an ASIC Formal Verification Engineer in Sunnyvale to shape AI/ML hardware acceleration. You will verify TPU architecture and its integration into AI/ML systems, contribute to project definitions, verification strategies, and silicon bring-up.

You’ll work with a team enabling data-center accelerators, implement formal verification for complex digital designs, and influence next-gen data-center technology at Google.