DSP/ASIC Verification Engineer—AI Accelerators

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a verification engineer to shape the future of TPU‑based AI/ML hardware acceleration in Sunnyvale, CA. You will verify complex DSP blocks and high‑speed PHY designs, using fixed‑point math and mixed‑signal co‑simulation to ensure robust performance.

You will define verification strategies for RTL and DSP cores, build scalable UVM environments, and collaborate across RTL, design, and firmware teams to deliver world‑class TPU technology for Google Cloud and consumer products.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8 years of design verification experience with DSP/communication focus.
• Experience scripting for automation (Python/Perl/Makefile).
• Master's or PhD preferred in EE/CE.
• RNM/SystemVerilog-AMS verification experience.
• Knowledge of adaptive equalization (FFE/DFE) and timing recovery.
• Python, MATLAB, or C/C++ for testbench automation.

Responsibilities

• Verify RTL against reference models (MATLAB/C++/SystemC) with bit-exact, fixed-point methods.
• Verify adaptive equalization loops (FFE/DFE) and timing recovery under impairments.
• Model and verify DSP-Analog Front End interfaces using RNM or SystemVerilog-AMS.
• Develop and maintain scalable UVM-based testbenches and assertions (SVA).

Skills

DV design verification

Scripting (Python/Perl/Makefile)

RNM verification

SystemVerilog-AMS

Adaptive equalization (FFE/DFE)

Python/MATLAB/C/C++ for testbenches

Education

Bachelor's degree in Electrical/Computer Engineering

Master's or PhD in Electrical/Computer Engineering

Tools

MATLAB

SystemVerilog

C/C++

Job description

Google is seeking a verification engineer to shape the future of TPU‑based AI/ML hardware acceleration in Sunnyvale, CA. You will verify complex DSP blocks and high‑speed PHY designs, using fixed‑point math and mixed‑signal co‑simulation to ensure robust performance.

You will define verification strategies for RTL and DSP cores, build scalable UVM environments, and collaborate across RTL, design, and firmware teams to deliver world‑class TPU technology for Google Cloud and consumer products.