TPU ASIC Formal Verification Engineer – AI Hardware

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google in Sunnyvale, CA is seeking an ASIC Formal Verification Engineer to shape TPU hardware acceleration. You will verify complex TPU architectures and contribute to data center accelerators with formal methods and rigorous verification.

The role involves defining verification plans, building reusable verification components, and collaborating across silicon teams to push AI/ML performance at scale.

Qualifications

• Bachelor's degree or equivalent experience in EE/CS.
• 4 years experience with formal and design verification.
• Experience with SystemVerilog or Verilog.
• Experience with formal verification tools (Jasper, VC Formal, Questa Formal, 360-DV).

Responsibilities

• Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
• Resolve difficult to verify properties.
• Contribute improvements to methodologies to enhance formal verification results.
• Architect and implement reusable formal verification components.

Skills

SystemVerilog/Verilog

Formal verification

Scripting languages

Communication skills

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Master's degree or PhD in Electrical/Computer Engineering or Computer Science

Tools

Jasper

VC Formal

Questa Formal

360-DV

Job description

Google in Sunnyvale, CA is seeking an ASIC Formal Verification Engineer to shape TPU hardware acceleration. You will verify complex TPU architectures and contribute to data center accelerators with formal methods and rigorous verification.

The role involves defining verification plans, building reusable verification components, and collaborating across silicon teams to push AI/ML performance at scale.