TPU ASIC Formal Verification Engineer

Google; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google is seeking an ASIC Formal Verification Engineer to shape and verify TPUs and AI/ML hardware acceleration. You will verify complex digital designs with a focus on TPU architecture and integration in AI/ML systems, contributing to project definitions, formal verification, and silicon bringup.

Join a team responsible for data-center accelerators and cutting-edge AI compute, collaborating with architecture and design teams to ensure high-coverage formal verification across multiple projects.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of experience in silicon development or ASIC/SoC design.
• Experience with SystemVerilog Assertions (SVA) and formal verification methods.

Responsibilities

• Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
• Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
• Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
• Maintain and enhance CI, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
• Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.

Skills

SystemVerilog Assertions

Formal verification

ASIC/SoC design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Master's degree or PhD in EE/CE/CS (emphasis on computer architecture)

Tools

Cadence Jasper Formal

Synopsys VC Formal

Siemens Questa Formal

Job description

Google is seeking an ASIC Formal Verification Engineer to shape and verify TPUs and AI/ML hardware acceleration. You will verify complex digital designs with a focus on TPU architecture and integration in AI/ML systems, contributing to project definitions, formal verification, and silicon bringup.

Join a team responsible for data-center accelerators and cutting-edge AI compute, collaborating with architecture and design teams to ensure high-coverage formal verification across multiple projects.