TPU ASIC Verification Lead — Equity, Bonus, Impact

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Sunnyvale is seeking an ASIC Design Verification Manager for TPU designs to shape AI/ML hardware acceleration. You will lead a team and own functional verification for key components, guiding development of infrastructure from subchip to full-chip levels.

You'll collaborate with front-end design, architecture, and performance teams to ensure architectural compliance, functional correctness, and meet performance goals.

Qualifications

• Bachelor's degree in EE/CE/CS or related field or equivalent practical experience.
• 10 years of verification experience using SystemVerilog and UVM.
• 3 years of people management experience.

Responsibilities

• Lead the functional verification team for TPU Compute, setting priorities and coaching.
• Define and drive verification strategies for complex compute subsystems for TPU.
• Architect scalable verification environments and reusable flows.
• Provide technical leadership, code reviews, and establish verification quality standards.
• Collaborate with architects and design leads to influence micro-architectural decisions.

Skills

Verification experience

Leadership

People management

Communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog

UVM

Job description

Google Sunnyvale is seeking an ASIC Design Verification Manager for TPU designs to shape AI/ML hardware acceleration. You will lead a team and own functional verification for key components, guiding development of infrastructure from subchip to full-chip levels.

You'll collaborate with front-end design, architecture, and performance teams to ensure architectural compliance, functional correctness, and meet performance goals.