TPU ASIC Design Verification Engineer

Google LLC; Sunnyvale (CA); Presencial; USD 138 000 - 197 000; Tempo integral

Resumo da oferta

Google LLC in Sunnyvale is hiring an ASIC Design Verification Engineer to shape TPU technology that powers AI/ML workloads. You will verify complex digital blocks and develop constrained-random test environments using SystemVerilog and UVM, collaborating across the verification lifecycle with design teams.

The role emphasizes contributing to the verification of TPU architecture within AI/ML-infused systems, with in-person interviews required in most cases.

Qualificações

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.

Responsabilidades

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Identify and write all types of coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Create a constrained-random verification environment using SystemVerilog and UVM.

Conhecimentos

Design verification

SystemVerilog/Verilog

Constrained-random verification

UVM

Formação académica

Bachelor's degree in EE/CE/CS or equivalent

Master's/PhD in EE/CE/CS (computational architecture focus)

Ferramentas

UVM

Verilog simulators

Descrição da oferta de emprego

Google LLC in Sunnyvale is hiring an ASIC Design Verification Engineer to shape TPU technology that powers AI/ML workloads. You will verify complex digital blocks and develop constrained-random test environments using SystemVerilog and UVM, collaborating across the verification lifecycle with design teams.

The role emphasizes contributing to the verification of TPU architecture within AI/ML-infused systems, with in-person interviews required in most cases.