A leading tech company in Sunnyvale is seeking an ASIC Formal Verification Engineer to shape the future of AI/ML hardware acceleration. You will drive the development of TPU technology, verifying complex digital designs, especially focusing on TPU architecture integration. An ideal candidate will have a strong background in silicon development, formal verification, and collaboration with architecture and design teams. This position offers a competitive salary range of $156,000-$229,000, plus bonuses and benefits.
Qualifications
8 years of experience in silicon development or ASIC/SoC design.
Experience with formal verification platforms and applications.
Strong knowledge in silicon-based ICs and chips.
Responsibilities
Define and drive formal verification sign-off across complex designs.
Architect and develop reusable formal testbenches and methodology flows.
Guide logic designers to incorporate formal methods effectively.
Skills
SystemVerilog Assertions (SVA)
Formal verification methods
Collaboration with Architecture and Design teams
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field
Master's degree or PhD in related fields (preferred)
Tools
Cadence Jasper
Synopsys VC Formal
Siemens Questa Formal
Job description
A leading tech company in Sunnyvale is seeking an ASIC Formal Verification Engineer to shape the future of AI/ML hardware acceleration. You will drive the development of TPU technology, verifying complex digital designs, especially focusing on TPU architecture integration. An ideal candidate will have a strong background in silicon development, formal verification, and collaboration with architecture and design teams. This position offers a competitive salary range of $156,000-$229,000, plus bonuses and benefits.