SoC Front-End Digital Design Engineer — Multimedia Lab

TikTok; San Jose, Northern (CA, KY); Hybrid; USD 162,000 - 317,000; Full time

Job summary

TikTok is seeking a Front-End/RTL engineer in San Jose to help define the architecture of SoC tops/subsystems and drive RTL implementation. You will collaborate with Verification, Backend, and Mid-end teams to support synthesis, SDC generation, STA, and power optimization.

Responsibilities include Lint/CDC/RDC checks, and contributing to low-power strategies with UPF flow, clock gating, and power gating. Strong Verilog/SystemVerilog mastery and scripting ability are required.

Qualifications

• Bachelor's degree or higher in Microelectronics, ICs, CS, EE or related field.
• 1+ years of experience in digital front-end design (or promising candidates).
• Mastery of Verilog/SystemVerilog and solid digital circuits foundation.
• Proficiency with front-end EDA tools (Spyglass, Design Compiler, PrimeTime).
• Scripting fluency (Python, Perl, Tcl, Makefile) for automation.

Responsibilities

• Architecture Design: Define architecture of SoC top/subsystems and evaluate PPA in early design.
• RTL Implementation: Write RTL code (Verilog/SystemVerilog) and maintain design docs.
• Front-End Quality Control: Perform Lint, CDC, and RDC checks for robustness.
• Cross-Functional Collaboration: Work with Verification, Backend, Mid-end to support Synthesis, SDC, STA, and power optimization.
• Low Power Design: Contribute to low-power strategies, clock/power gating, and UPF flow.

Skills

Verilog/SystemVerilog

Python scripting

Education

Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field

Tools

Spyglass

Design Compiler

PrimeTime

Job description

TikTok is seeking a Front-End/RTL engineer in San Jose to help define the architecture of SoC tops/subsystems and drive RTL implementation. You will collaborate with Verification, Backend, and Mid-end teams to support synthesis, SDC generation, STA, and power optimization.

Responsibilities include Lint/CDC/RDC checks, and contributing to low-power strategies with UPF flow, clock gating, and power gating. Strong Verilog/SystemVerilog mastery and scripting ability are required.