SoC Physical Design Architect - Tapeout Lead

Astera Labs; San Jose (CA); Hybrid; USD 185,000 - 240,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs in San Jose, CA, is seeking a Principal Physical Design Engineer to own RTL2GDS for high-performance connectivity SoCs, driving floorplan, timing, power, and signoff from RTL to tapeout.

You will lead physical design methodology, mentor engineers, and collaborate with RTL, DFT, analog, and package teams to deliver next-generation silicon on 7nm or below nodes, with full-chip signoff and tapeout support.

Qualifications

• Experience with RTL-to-GDS flow for advanced nodes (7nm or below).
• Strong command of low-power techniques and signoff flows.
• Proven track record delivering high-frequency, complex SoCs to tapeout.

Responsibilities

• Own end-to-end RTL2GDS flow and tapeout support.
• Drive floorplan, placement, CTS, routing, and signoff on advanced nodes.
• Optimize block- and chip-level P&R and routing convergence.
• Architect clock topology to meet skew and power targets.
• Lead tapeout and ECO closure through fab handoff.
• Conduct timing, power, and signoff analyses.
• Lead multi-mode multi-corner STA and UPF/CPF flows.
• Oversee LVS/DRC/antenna checks and reliability signoff.
• Mentor engineers and drive design reviews across teams.
• Define ECO flow methodologies and full-chip signoff processes.

Skills

RTL2GDS ownership

Synthesis & P&R

Clock tree synthesis

Timing closure

Power integrity

UPF/CPF for low-power

Tcl/Python scripting

Team leadership

Education

Bachelor's degree in Electrical Engineering or related field

MS in Electrical Engineering

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

PrimeTime

Scripting: Tcl/Python

Job description

Astera Labs in San Jose, CA, is seeking a Principal Physical Design Engineer to own RTL2GDS for high-performance connectivity SoCs, driving floorplan, timing, power, and signoff from RTL to tapeout.

You will lead physical design methodology, mentor engineers, and collaborate with RTL, DFT, analog, and package teams to deliver next-generation silicon on 7nm or below nodes, with full-chip signoff and tapeout support.