Senior Physical Design Engineer – Tapeout Leader

Celero Communications; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications in Irvine, CA is seeking an experienced Physical Design Engineer to lead physical implementation of SoCs, including floorplanning, power planning, P&R, CTS, timing closure, and sign-off.

Collaborate with architecture, RTL, circuit and verification teams to deliver high-performance chips; mentor engineers and define physical design methodologies to ensure tape-out of next-generation semiconductor products.

Qualifications

• 7+ years of ASIC physical design experience
• Tapeout experience in advanced nodes (7nm/5nm/3nm)
• Deep knowledge of PPA, timing, and EM/IR cleanup
• Experience with industry-standard EDA tools and flows

Responsibilities

• RTL-to-GDSII execution for SoCs or complex blocks
• Design optimization: floorplanning, power grid, CTS
• Resolve timing, congestion, EM/IR issues with frontend teams
• Signoff & verification: STA, DRC/LVS checks
• Develop and improve physical design methodologies and automation
• Mentor engineers and coordinate with architecture, RTL and analog teams

Skills

ASIC physical design

Floorplanning & P&R

STA/DRC/LVS

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Cadence Pegasus

Cadence Calibre

Job description

Celero Communications in Irvine, CA is seeking an experienced Physical Design Engineer to lead physical implementation of SoCs, including floorplanning, power planning, P&R, CTS, timing closure, and sign-off.

Collaborate with architecture, RTL, circuit and verification teams to deliver high-performance chips; mentor engineers and define physical design methodologies to ensure tape-out of next-generation semiconductor products.