Senior Physical Design Lead — Tapeout Expert

Normal Computing Corp.; Mountain View, New York (CA, NY); On-site; USD 220,000 - 300,000; Full time

Job summary

Normal Computing in Mountain View, CA, seeks a seasoned Physical Design Lead to own the silicon realization path from synthesis to GDSII tapeout. You will drive floorplanning, P&R, CTS, STA, and signoff with RTL and architecture teams to achieve aggressive PPA targets.

You will lead the PD team, plan projects, select EDA tools, and ensure design feasibility across the backend flow. A tapeout track record and 7+ years in leadership are required.

Qualifications

• Lead at least 3+ tapeouts from netlist to signoff for advanced nodes.
• Deep hands-on experience with floorplanning, P&R, CTS, and signoff timing closure.

Responsibilities

• Lead the full netlist-to-GDSII physical design flow across floorplanning, power grid design, placement, CTS, and P&R.
• Own static timing analysis (STA) and timing closure across corners/modes.
• Drive power, area, and signal integrity optimization for PPA and crosstalk analysis.
• Execute full chip/block physical signoff checks (DRC/LVS/ERC) and guide post-silicon debugging.
• Manage tapeout checklists and post-silicon bring-up support.

Skills

Tapeout Track Record

PD Flow Expertise

Backend Debugging Instincts

Cross-Functional Feasibility

Managerial experience

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Pegasus

Calibre

Job description

Normal Computing in Mountain View, CA, seeks a seasoned Physical Design Lead to own the silicon realization path from synthesis to GDSII tapeout. You will drive floorplanning, P&R, CTS, STA, and signoff with RTL and architecture teams to achieve aggressive PPA targets.

You will lead the PD team, plan projects, select EDA tools, and ensure design feasibility across the backend flow. A tapeout track record and 7+ years in leadership are required.