Staff Physical Design Engineer: 5nm Tapeout & AI-Driven

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

Wellness and financial benefits

Salary range discussed with recruiter

Job summary

Synopsys Inc. is seeking a senior ASIC/physical design engineer to help customers achieve tapeout-ready implementations. You will work on RTL-to-GDS flows, using Fusion Compiler and related tools, across advanced nodes and high-performance applications.

You will provide technical guidance, automate tasks with TCL/Python, and collaborate with R&D to address real customer issues, ensuring quality and timely design closures.

Qualifications

• 5+ years in ASIC/physical design or CAD engineering.
• Experience with RTL-to-GDS flows including synthesis, place-and-route, timing closure.
• Proficiency with Fusion Compiler and related signoff tools.
• Understanding of timing, power, congestion, routing and design closure.
• Scripting in TCL and Python to automate tasks; ability to work across time zones.

Responsibilities

• Support customers through physical design implementation and design closure with Synopsys tools.
• Debug timing, power, area, congestion, routing and runtime optimization at advanced nodes (5nm+).
• Guide customers to achieve implementation closure within tapeout schedules.
• Provide best-practice guidance for synthesis, place-and-route, timing closure and power optimization.
• Build TCL automation scripts to streamline workflows and speed up engagements.
• Leverage AI-assisted workflows to improve productivity and issue resolution.
• Collaborate with internal R&D to reproduce issues and feed real-world use cases to product teams.
• Present technical solutions to senior customer engineers and design leads during critical phases.

Skills

RTL-to-GDS flow

Fusion Compiler

Scripting: TCL/Python

Advanced-node implementation

Education

Bachelors in Electrical/Computer Engineering

Tools

Formality

PrimeTime

ICC2

Job description

Synopsys Inc. is seeking a senior ASIC/physical design engineer to help customers achieve tapeout-ready implementations. You will work on RTL-to-GDS flows, using Fusion Compiler and related tools, across advanced nodes and high-performance applications.

You will provide technical guidance, automate tasks with TCL/Python, and collaborate with R&D to address real customer issues, ensuring quality and timely design closures.