Senior Physical Design Engineer — Tapeout Expert

Normal Computing Corp.; Mountain View (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Normal Computing is seeking a seasoned Physical Design Engineer to own end-to-end silicon realization at Mountain View, CA. You will drive floorplanning, placement, CTS, and P&R to achieve aggressive PPA targets, collaborating with RTL and architecture teams to ensure feasibility.

You will manage signoff, DRC/LVS, and tapeout readiness, delivering tapeout-proven execution across advanced nodes while supporting post-silicon debugging and bring-up as needed.

Qualifications

• 3+ successful tapeouts from netlist to signoff.
• Hands-on experience with full-backend flow tools.
• Strong debugging skills for STA, IR/EM, and DRC/LVS.

Responsabilités

• Lead the netlist-to-GDSII physical design flow from floorplanning to tapeout.
• Drive CTS, P&R, and signoff timing across corners and modes.
• Optimize power, performance, and area (PPA) while ensuring signal integrity.
• Perform full chip/ block signoff checks and prepare handoff to foundry.
• Collaborate with RTL, architecture, and DFT teams on feasibility.

Connaissances

Tapeout Track Record

PD Flow Experience

Backend Debugging

Cross-Functional Collaboration

Outils

Innovus

IC Compiler II

Tempus

PrimeTime

Calibre

Description du poste

Normal Computing is seeking a seasoned Physical Design Engineer to own end-to-end silicon realization at Mountain View, CA. You will drive floorplanning, placement, CTS, and P&R to achieve aggressive PPA targets, collaborating with RTL and architecture teams to ensure feasibility.

You will manage signoff, DRC/LVS, and tapeout readiness, delivering tapeout-proven execution across advanced nodes while supporting post-silicon debugging and bring-up as needed.