Senior Physical Design Engineer - Tapeout & PPA Focus

TSMC; San Jose (CA); On-site; USD 110,000 - 160,000; Full time

Job summary

TSMC in San Jose seeks an experienced physical design engineer to drive end-to-end tapeout on cutting-edge nodes. You will manage floorplanning, power integrity, CTS, and routing, while optimizing PPA and performing extensive signoff analyses.

You will also develop CAD automation scripts (Python, TCL) and work with RTL, DFT, and CAD teams to ensure successful integration across the design flow in a fast-paced environment.

Qualifications

• Master’s Degree or higher in Electrical Engineering or Computer Science with strong VLSI coursework.
• Minimum of 3 years of industrial experience in physical design or related semiconductor field.
• Deep understanding of full physical design flow (auto placement and route, STA, layout design, physical verification, IREM signoff).
• Hands-on experience with major EDA tools from Synopsys and Cadence.
• Proficiency in Python, TCL, shell scripting, Verilog.
• Strong analytical and problem-solving skills with attention to detail.
• Excellent written and verbal communication; collaborative team player.

Responsibilities

• Drive end-to-end physical implementation and tapeout of test vehicles on leading-edge process nodes (A16/A14/A10).
• Execute flows from netlist-to-GDS, including floorplanning, power grid, low-power integration.
• Perform advanced placement, CTS, and routing for performance and congestion management.
• Optimize power, performance, and area (PPA) targets; conduct RC extraction and signoff analyses.
• Develop CAD automation scripts and dashboards (TCL, Python, CSH) to streamline design flows.
• Collaborate with RTL, DFT, and CAD teams to ensure seamless integration.

Skills

Digital circuits

Python scripting

TCL scripting

Verilog

Unix shell

Analytical skills

Communication skills

Education

Master’s degree in EE/CS

Tools

Synopsys ICC2

Synopsys DC

PrimeTime

StarRC

ICV

Cadence Innovus

Cadence Virtuoso

Cadence SimVision

Ansys Redhawk

Fusion Compiler

Job description

TSMC in San Jose seeks an experienced physical design engineer to drive end-to-end tapeout on cutting-edge nodes. You will manage floorplanning, power integrity, CTS, and routing, while optimizing PPA and performing extensive signoff analyses.

You will also develop CAD automation scripts (Python, TCL) and work with RTL, DFT, and CAD teams to ensure successful integration across the design flow in a fast-paced environment.