Senior Physical Design Engineer for SoC Tapeout

Rivian Automotive; Palo Alto (CA); Sur place; USD 186 000 - 232 000; Plein temps

Résumé du poste

Rivian Automotive in the San Francisco Bay Area seeks a senior Physical Design Engineer to drive all phases of physical design for high-performance SoCs, from RTL to GDSII, collaborating with Foundry, SoC Architect, and Power Integrity teams to ensure a successful tapeout.

You will lead floorplanning, clock planning, and DFT strategy while ensuring power integrity, EM-IR sign-off, and robust timing for production silicon in a cutting-edge environment.

Qualifications

• 12+ years of experience in the chip industry with a track record of delivering silicon into volume production across multiple technology generations.
• Proven track record of SoC definition of complex SoCs over multiple technology generations.
• Experience with advanced process nodes (5nm and below) and DRC/DFM challenges.
• Strong teamwork and leadership qualities with references.
• Solid background in physical design from block to full-chip level.

Responsabilités

• Perform subchip and block level place and route to meet performance, power and area targets.
• Lead full chip SoC integration activities including floorplanning, IP integration, clock planning and power integrity analysis.
• Use EDA tools for timing, power, DRC/LVS verification and EM-IR sign-off workflows.
• Develop and support CPA/CPM analyses for package and die co-design.
• Collaborate with Foundry, Microarchitecture and Packaging teams to ensure robust floorplans and power delivery.

Connaissances

Physical design

Clock tree synthesis

STA timing

Voltage drop analysis

Python/TCL scripting

Formation

BS/MS/PhD in Electrical and Computer Engineering

Outils

Synopsys Cadence tools

Description du poste

Rivian Automotive in the San Francisco Bay Area seeks a senior Physical Design Engineer to drive all phases of physical design for high-performance SoCs, from RTL to GDSII, collaborating with Foundry, SoC Architect, and Power Integrity teams to ensure a successful tapeout.

You will lead floorplanning, clock planning, and DFT strategy while ensuring power integrity, EM-IR sign-off, and robust timing for production silicon in a cutting-edge environment.