Senior STA Physical Design Engineer - PnR & Signoff Expert

Astera Labs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Senior Principal STA Physical Design Engineer to drive RTL-to-GDS sign-off for its connectivity ASICs used by major cloud providers and OEMs. On-site in San Jose, you will collaborate with RTL, verification, and frontend teams to ensure robust, scalable sign-off across complex designs.

You’ll bring deep PnR, timing, and EM-IR experience, with strong scripting skills and a track record of handling high-speed transceiver timing challenges in advanced nodes.

Qualifications

• Bachelor’s degree in electrical engineering or computer science.
• 10+ years of PnR and sign-off experience for complex SoCs in relevant domains.
• Expertise with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting skills in Tcl, Python or Perl.
• Ability to work independently with strong prioritization and customer focus.

Responsibilities

• Drive PnR activities from RTL to GDS and ensure robust signoff across complex SoCs or sub-systems.
• Identify RTL issues early and work with frontend team on resolution.
• Hands-on experience with various custom clocking techniques.
• Experience with high-speed designs with SERDES and DDR IPs.
• Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS.
• Hands-on ECO flow experience using PrimeTime DMSA and hyperscale models for large chips.
• Understand SDC constraints and refine with design teams.
• Collaborate with top-level owners on I/O timing budgets across designs.

Skills

PnR expertise

Synthesis

Place-and-Route

Sign-off

Tcl/Python scripting

Education

Bachelors in Electrical Engineering or Computer Science

Master's degree preferred

Tools

Cadence tools

Synopsys tools

PrimeTime (PT) scripting

Job description

Astera Labs is seeking a Senior Principal STA Physical Design Engineer to drive RTL-to-GDS sign-off for its connectivity ASICs used by major cloud providers and OEMs. On-site in San Jose, you will collaborate with RTL, verification, and frontend teams to ensure robust, scalable sign-off across complex designs.

You’ll bring deep PnR, timing, and EM-IR experience, with strong scripting skills and a track record of handling high-speed transceiver timing challenges in advanced nodes.