Principal Physical Design Engineer – Tapeout & Timing Lead

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal Physical Design Engineer to own the RTL2GDS flow for high-performance connectivity SoCs. You will drive floorplanning, placement, CTS, routing, and signoff on advanced nodes, coordinating with RTL, DFT, analog, and package teams.

You will mentor engineers, define scalable methodologies, and lead tapeout execution from RTL to tapeout, ensuring PPA and time-to-market goals are met for AI-scale systems.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering required.
• 8+ years of physical design with multiple tapeouts on advanced nodes.
• Proficiency with industry-standard tools for synthesis, place & route, timing.
• Experience with low-power techniques and UPF/CPF.

Responsibilities

• End-to-End RTL2GDS ownership across the flow.
• Own RTL2GDS flow: synthesis, floorplan, placement, CTS, routing, signoff.
• Drive block- and chip-level place and route strategy and convergence.
• Architect clock tree synthesis to meet skew and power targets.
• Lead tapeout execution including ECO closure and GDS handoff.
• Drive timing, power, and signoff; perform STA across corners.
• Own LVS/DRC/antenna and reliability signoff through closure.
• Mentor engineers and evolve physical design methodologies.

Skills

RTL2GDS ownership

High-frequency design

Tcl/Python scripting

Low-power techniques

Mentoring / leadership

Education

Bachelor's degree in Electrical or Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler / ICC2

Cadence Innovus

PrimeTime

Job description

Astera Labs is seeking a Principal Physical Design Engineer to own the RTL2GDS flow for high-performance connectivity SoCs. You will drive floorplanning, placement, CTS, routing, and signoff on advanced nodes, coordinating with RTL, DFT, analog, and package teams.

You will mentor engineers, define scalable methodologies, and lead tapeout execution from RTL to tapeout, ensuring PPA and time-to-market goals are met for AI-scale systems.