SoC Digital Design Engineer for Low-Power AI Accelerators

Meta; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Meta in Sunnyvale, CA is seeking a Digital Design Engineer to contribute to the development of advanced hardware accelerators, SoCs, and custom silicon. You will work with researchers and engineers to implement low-power designs, map algorithms to hardware, and participate in IP/sub-system integration.

The role requires a strong background in digital design, RTL coding, and micro-architecture, with hands-on experience shipping production silicon.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a related field.
• 6+ years of hardware design experience for production silicon shipped in volume.
• Experience with ASIC/SoC development and RTL implementations.

Responsibilities

• Contribute to ASIC digital μArchitecture and design.
• Assist in performance and power analysis to meet targets.
• Map algorithms onto hardware and specify IP/subsystems integration requirements.
• Collaborate with Verification, Physical Design, and Design for Test teams.

Skills

RTL coding

Digital design

Micro-architecture

Power analysis

Education

BSc CS/CE or related field

Job description

Meta in Sunnyvale, CA is seeking a Digital Design Engineer to contribute to the development of advanced hardware accelerators, SoCs, and custom silicon. You will work with researchers and engineers to implement low-power designs, map algorithms to hardware, and participate in IP/sub-system integration.

The role requires a strong background in digital design, RTL coding, and micro-architecture, with hands-on experience shipping production silicon.