ASIC Engineer, Design

Anysilicon; Sunnyvale (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Meta in Sunnyvale, CA seeks skilled Design Engineers to develop advanced hardware accelerators and ASIC IPs for ML, graphics, display, and network acceleration. You will work with top researchers to build low-power solutions and collaborate across DV, PD, and architecture teams.

The role emphasizes micro-architecture, RTL coding, and verification for complex IPs, with hands-on collaboration for design targets related to performance and power optimization.

Qualifications

• Experience in digital design microarchitecture and RTL coding.
• Ability to map algorithms to hardware and specify IP/sub-system integration.
• Strong communication and collaboration skills.

Responsibilities

• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Collaborate with architects to map algorithms onto hardware and specify integration requirements.
• Assist in performance and power analysis to meet targets.
• Coordinate with Verification, Physical Design, and Design-for-Test teams.
• Drive IP/sub-system micro-architecture and RTL design with DV/PD leads.

Skills

Digital design

RTL coding

SoC integration

Microarchitecture

Tools

Synthesis

Timing Closure

Formal Verification

Job description

Meta, 1180 Discovery Way, Sunnyvale, CA 94089

Job Description:

Meta is looking for skilled Design Engineers to develop advanced technology solutions, focusing on machine learning, graphics, display, and network acceleration. The role involves collaboration with top researchers and engineers to create low-power hardware accelerators and custom silicon solutions for innovative devices.

Responsibilities:

• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Collaborate with architects to map algorithms onto hardware and specify requirements for IP and subsystems integration.
• Assist in performance and power analysis to meet design targets.
• Work with teams such as Verification, Physical Design, and Design-for-Test.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Qualifications:

• Experience in digital design microarchitecture, RTL coding, SoC integration, and micro-architecture development.
• Demonstrated communication and collaboration skills.

Skills:

• Experience in CPU, NOC, Memory, Die-to-die, and Peripheral Subsystems.
• Knowledge of Synthesis, Timing Closure, and Formal Verification Methodology.
• Experience managing SOC-level boot flow and Silicon Debug architectures.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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