Senior Digital Design Engineer, Interconnect & SoC

Meta; Sunnyvale, Northern (CA, KY); Hybride; USD 150 000 - 230 000; Plein temps

Résumé du poste

Meta seeks a seasoned Digital Design Engineer in Sunnyvale, CA to contribute to ASIC digital architectures and RTL implementation. You will partner with researchers and engineers to optimize low-power accelerators and SoCs, aligning IP blocks with design goals and performance targets.

The role emphasizes cross-functional collaboration with Verification, Physical Design, and Design-for-Test teams, plus hands-on micro-architecture and verification development for complex IPs.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8+ years of hardware design experience for production silicon.
• Experience in digital design micro-architecture, RTL coding, and micro-architecture development.

Responsabilités

• Contribute to ASIC digital μArchitecture and design.
• Assist performance/power analysis of the design and help meet power and performance targets.
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Connaissances

Digital micro-architecture

RTL coding

Design verification

Performance/power analysis

IP/sub-system integration

Formation

Bachelor's degree in Computer Science or Electrical Engineering

Description du poste

Meta seeks a seasoned Digital Design Engineer in Sunnyvale, CA to contribute to ASIC digital architectures and RTL implementation. You will partner with researchers and engineers to optimize low-power accelerators and SoCs, aligning IP blocks with design goals and performance targets.

The role emphasizes cross-functional collaboration with Verification, Physical Design, and Design-for-Test teams, plus hands-on micro-architecture and verification development for complex IPs.