Digital Design Engineer, Interconnect

Meta; Sunnyvale, Northern (CA, KY); On-site; USD 150,000 - 230,000; Full time

Job summary

Meta seeks a seasoned Digital Design Engineer in Sunnyvale, CA to contribute to ASIC digital architectures and RTL implementation. You will partner with researchers and engineers to optimize low-power accelerators and SoCs, aligning IP blocks with design goals and performance targets.

The role emphasizes cross-functional collaboration with Verification, Physical Design, and Design-for-Test teams, plus hands-on micro-architecture and verification development for complex IPs.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8+ years of hardware design experience for production silicon.
• Experience in digital design micro-architecture, RTL coding, and micro-architecture development.

Responsibilities

• Contribute to ASIC digital μArchitecture and design.
• Assist performance/power analysis of the design and help meet power and performance targets.
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Skills

Digital micro-architecture

RTL coding

Design verification

Performance/power analysis

IP/sub-system integration

Education

Bachelor's degree in Computer Science or Electrical Engineering

Job description

# Digital Design Engineer, InterconnectSunnyvale, CA+2 locationsHardware+ 1 moreApply nowMeta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.---## Digital Design Engineer, Interconnect Responsibilities* Contribute to ASIC digital μArchitecture and design* Assist performance/power analysis of the design and help meet power and performance targets* Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration* Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test* Develop micro-architecture, RTL coding, and design verification for complex IPs* Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads## Minimum Qualifications* Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience* 8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume* Experience in digital design μArchitecture, RTL coding, and micro-architecture development* Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams