ASIC Engineer, Design

Meta; Sunnyvale (CA); Vor Ort; USD 146.000 - 209.000; Vollzeit

Benefits dieser Stelle

Bonus

Equity

Benefits

Zusammenfassung

Meta is seeking highly skilled Design Engineers to join our team in Sunnyvale, CA. You will contribute to the development of advanced technology solutions including machine learning, graphics, display, and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon that enable the next generation of innovative devices. Minimum qualifications include a Bachelor's degree and 6+ years in hardware design for production

Qualifikationen

• Bachelor's degree in CS/Engineering or equivalent practical experience.
• 6+ years of hardware design experience for production silicon.
• Experience in digital design micro-architecture, RTL, SoC integration.
• Strong communication and collaboration skills.

Aufgaben

• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Map algorithms onto hardware and specify integration requirements.
• Assist performance and power analysis to meet targets.
• Collaborate with Verification, Physical Design, and DFT teams.
• Drive IP/sub-system micro-architecture and RTL design with DV/PD leads.

Kenntnisse

ASIC Design

RTL coding

Hardware design

Communication

Ausbildung

Bachelor's degree in Computer Science/Engineering

Tools

Synthesis

Timing Closure

Formal Verification

Jobbeschreibung

Summary:

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning, graphics, display, and network acceleration. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Required Skills:

ASIC Engineer, Design Responsibilities:

1. Develop micro-architecture, RTL coding, and design verification for complex IPs.
2. Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
3. Assist performance/power analysis of the design and help meet power and performance targets.
4. Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
5. Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
3. Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development
4. Demonstrated communication and collaboration skills

Preferred Qualifications:

Preferred Qualifications:

1. Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
2. Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems
3. Experience with Synthesis, Timing Closure and Formal Verification Methodology
4. Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architectures

Public Compensation:

$146,000/year to $209,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affi...

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