Senior GFX/Display IP ASIC Design Engineer

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking experienced Design Engineers to contribute to advanced hardware solutions, including ML accelerators and custom silicon. You will work with researchers and engineers to design, implement, and optimize low-power accelerators and state-of-the-art SoCs for next-generation devices.

The role requires a strong background in digital design and RTL, with collaboration across Verification, Physical Design, and Architecture teams.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 6+ years of Hardware Design experience shipping production silicon.
• Experience in digital design architecture, RTL coding, and micro-architecture development.
• Experience communicating technical design decisions to cross-functional partners.

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis to meet targets.
• Map algorithms onto hardware and specify IP/subsystems requirements.
• Collaborate with Verification, Physical Design, and Design-for-Test teams.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design with DV and PD leads.

Skills

Digital design architecture

RTL coding

Micro-architecture development

Cross-functional collaboration

Programming (C/C++/Python)

Synthesis & timing analysis

Power/ performance optimization

Education

Bachelor's degree in CS/CE or equivalent

Tools

EDA tools

Job description

Meta is seeking experienced Design Engineers to contribute to advanced hardware solutions, including ML accelerators and custom silicon. You will work with researchers and engineers to design, implement, and optimize low-power accelerators and state-of-the-art SoCs for next-generation devices.

The role requires a strong background in digital design and RTL, with collaboration across Verification, Physical Design, and Architecture teams.