RTL Design Engineer for ML Accelerators & ASICs

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Bonus target

Job summary

Google Sunnyvale, CA is seeking a mid-level RTL Design Engineer to shape AI/ML hardware accelerators. You will work on TPU architecture, verify complex digital designs, and collaborate with software teams to deliver high-performance AI workloads.

Requirements include a Bachelor's in EE/CE/CS, 4 years of custom silicon design, RTL design with Verilog/SystemVerilog, and a strong systems mindset. Preferred candidates have advanced degrees and experience in high-performance, low-power design

Qualifications

• Bachelor's degree or equivalent practical experience.
• 4 years of custom silicon design experience (e.g., SoCs, ASICs).
• RTL design experience with Verilog/SystemVerilog.

Responsibilities

• Understand the overall application of the chip and propose design improvements.
• Design and document ASIC blocks, including functionality and timing.
• Work with software teams on interfaces and documentation.

Skills

RTL design

Verilog/SystemVerilog

Python/Perl scripting

Cross-functional collaboration

TPU/ML accelerator knowledge

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD preferred

Job description

Google Sunnyvale, CA is seeking a mid-level RTL Design Engineer to shape AI/ML hardware accelerators. You will work on TPU architecture, verify complex digital designs, and collaborate with software teams to deliver high-performance AI workloads.

Requirements include a Bachelor's in EE/CE/CS, 4 years of custom silicon design, RTL design with Verilog/SystemVerilog, and a strong systems mindset. Preferred candidates have advanced degrees and experience in high-performance, low-power design