Silicon Engineer: ML/Video Acceleration ASIC Design

Meta; Sunnyvale (CA); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking ASIC Design Engineers within the Infrastructure organization to build cutting edge ASICs for ML, video transcoding, and network acceleration in Sunnyvale, CA. You will explore architectures and develop micro-architectures, identifying and integrating IP while coordinating with verification and implementation teams to meet timing and power targets.

The role requires a BS in CS/CE or related field, 2+ years in relevant RTL/micro-architecture, and proficiency with Verilog,

Qualifications

• Bachelor's degree in CS/CE or related field, completed before joining Meta.
• 2+ years in micro-architecture and RTL development for complex IPs OR experience in SoC micro-architecture, design and integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration.
• Micro-architecture development.
• Soft and hard IP identification, selection and integration; collaboration with verification and emulation teams in test plan development and debug.
• Collaboration with implementation team to close the design on timing and power.

Skills

RTL development

Micro-architecture

IP integration

Synthesis

Timing closure

Formal verification

CPU/NOC/Memory subsystems

Education

Bachelor's degree in CS/CE or related field

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is seeking ASIC Design Engineers within the Infrastructure organization to build cutting edge ASICs for ML, video transcoding, and network acceleration in Sunnyvale, CA. You will explore architectures and develop micro-architectures, identifying and integrating IP while coordinating with verification and implementation teams to meet timing and power targets.

The role requires a BS in CS/CE or related field, 2+ years in relevant RTL/micro-architecture, and proficiency with Verilog,