RTL Design Engineer for AI Accelerator SoC

Mentium Technologies Inc.; Santa Barbara (CA); On-site; USD 140,000 - 220,000; Full time

Benefits offered by this job

401(k)

Flexible PTO

Full PPO medical, dental, and vision

Job summary

Mentium Technologies Inc. seeks an experienced ASIC RTL Design Engineer to design, implement and test complex digital RTL components for its AI accelerator. You will collaborate with system architects, verification, physical design, and software teams to meet stringent PPA goals.

Join a forward‑looking team working on vision AI accelerators, machine learning algorithms, and a hardware-software library. The role emphasizes RTL/verification excellence and integration with PCIe IP within a SOC.

Qualifications

• Master’s or PhD in Electrical/Computer Engineering or related field.
• 5+ years RTL design experience with 2+ years in industry.
• Strong background in digital design principles, FSMs, and CDC.
• Proficiency in SystemVerilog.
• Experience with front-end EDA tools (e.g., Synopsys, Cadence) including simulators, linters, and CDC checkers.
• Knowledge of synthesis, static timing analysis, DFT, and ECO flows.
• Scripting (Perl, Python) for automation and productivity enhancements.
• Basic knowledge of memory compilers, deep learning algorithms and neural networks.

Responsibilities

• Manage and develop RTL components for complex systems and AI accelerators.
• Define detailed micro-architectures based on high-level product specifications and requirements.
• Write clean, efficient, synthesizable and reusable Verilog/SystemVerilog code with a focus on meeting frequency, power, and area targets.
• Help with Integrating complex IPs (e.g., PCIe) into SoCs and perform relevant front-end integration activities (lint, CDC checks, synthesis, ECO).
• Work with verification teams to develop meaningful SystemVerilog assertions, constraints, checkers, and test benches.
• Debug RTL code using modern simulation tools and waveform viewers, ensuring coverage closure and functional correctness.
• Collaborate on timing closure with physical design teams, optimizing for performance, power, and area.
• Coordinate with system architects to align design specifications and functional requirements.
• Collaborate with physical design teams on synthesis, static timing, DFT, and ECO processes.
• Perform power, performance, and area (PPA) trade-offs and drive architectural decisions to meet aggressive project goals.

Skills

RTL design

SystemVerilog

FSM

CDC

Perl/Python scripting

EDA tools

Education

Master's or PhD in Electrical/Computer Engineering

Tools

Synopsys Cadence

Simulation Tools

Memory compilers

Job description

Mentium Technologies Inc. seeks an experienced ASIC RTL Design Engineer to design, implement and test complex digital RTL components for its AI accelerator. You will collaborate with system architects, verification, physical design, and software teams to meet stringent PPA goals.

Join a forward‑looking team working on vision AI accelerators, machine learning algorithms, and a hardware-software library. The role emphasizes RTL/verification excellence and integration with PCIe IP within a SOC.