Senior ASIC Design Engineer – SoC, RTL & IP Acceleration

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking highly skilled Design Engineers to join our team in Sunnyvale, CA. You will contribute to the development of advanced technology solutions including machine learning, graphics, display, and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon that enable the next generation of innovative devices. Minimum qualifications include a Bachelor's degree and 6+ years in hardware design for production

Qualifications

• Bachelor's degree in CS/Engineering or equivalent practical experience.
• 6+ years of hardware design experience for production silicon.
• Experience in digital design micro-architecture, RTL, SoC integration.
• Strong communication and collaboration skills.

Responsibilities

• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Map algorithms onto hardware and specify integration requirements.
• Assist performance and power analysis to meet targets.
• Collaborate with Verification, Physical Design, and DFT teams.
• Drive IP/sub-system micro-architecture and RTL design with DV/PD leads.

Skills

ASIC Design

RTL coding

Hardware design

Communication

Education

Bachelor's degree in Computer Science/Engineering

Tools

Synthesis

Timing Closure

Formal Verification

Job description

Meta is seeking highly skilled Design Engineers to join our team in Sunnyvale, CA. You will contribute to the development of advanced technology solutions including machine learning, graphics, display, and network acceleration.

You will design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon that enable the next generation of innovative devices. Minimum qualifications include a Bachelor's degree and 6+ years in hardware design for production