SoC DFT Engineer: Automation & Debug Expert

Broadcom; San Jose (CA); On-site; USD 69,000 - 110,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Annual equity awards

401(k) matching

ESPP

Comprehensive benefits

Job summary

Broadcom, Inc. seeks a DFT Engineer at its San Jose Development Center to implement, verify, and debug SoC DFT with guidance from senior engineers.

Responsibilities include test insertion, ATPG vector generation, silicon bring-up, STA collaboration, and automation of DFT flows; requires TCL/Perl/Python/C++/Verilog coding in a Linux environment.

Qualifications include EE/CE degree, knowledge of Scan/ATPG/BIST/JTAG, Verilog, testbench, and strong problem-solving skills.

Qualifications

• Strong foundation in electrical engineering and digital/analog circuit design principles.
• Relevant coursework in Digital Logic Design, VLSI Design, Computer Architecture, and Circuit Theory.
• Basic understanding of DFT concepts such as Scan, ATPG, BIST, and JTAG.
• Experience with Verilog HDL coding, testbench development, and simulation tools.
• Familiarity with scripting languages (Python, Perl, Tcl, or C++) in a Linux environment.
• Excellent problem-solving, analytical, and communication skills.

Responsibilities

• Assist with DFT implementation, including Scan, MBIST, TAP, and IO integration.
• Support ATPG vector generation, simulation, and verification at the ASIC/Chip level.
• Help debug test vectors before tape release and during ATE silicon bring-up.
• Work closely with senior engineers on STA and design closure for test.
• Automate DFT flows and scripts for improved engineering efficiency.

Skills

TCL

Perl

Python

C++

Verilog

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Testbench development

Simulation tools

Linux environment

Job description

Broadcom, Inc. seeks a DFT Engineer at its San Jose Development Center to implement, verify, and debug SoC DFT with guidance from senior engineers.

Responsibilities include test insertion, ATPG vector generation, silicon bring-up, STA collaboration, and automation of DFT flows; requires TCL/Perl/Python/C++/Verilog coding in a Linux environment.

Qualifications include EE/CE degree, knowledge of Scan/ATPG/BIST/JTAG, Verilog, testbench, and strong problem-solving skills.