Senior DFT Engineer for SoC/ASIC Testing

Avinyaa Technologies, LLC.; Sunnyvale (CA); On-site; USD 83,000 - 90,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA seeks a DFT Engineer to define and execute robust DFT strategies for high‑performance SoCs/ASICs. You will work with front-end design, physical design, verification, and product engineering to ensure high test coverage and streamlined post‑silicon test enablement.

Key responsibilities include implementing DFT architectures (Scan, ATPG, MBIST, IJTAG), performing scan insertion and optimization, and integrating MBIST controllers.

Qualifications

• 3+ years hands-on DFT experience in advanced SoC/ASIC development.
• Verilog/SystemVerilog proficiency for DFT integration and simulation debugging.
• Scan synthesis and boundary scan integration experience.
• ATPG pattern generation, debugging, and fault-grading experience.
• MBIST architecture and memory repair experience.
• Knowledge of IEEE 1149.1/JTAG and related test logic.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG (IEEE 1149.1/1500/1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization for timing closure and power grid compatibility.
• Integrate MBIST controllers, repair mechanics, and memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation with SDF timing.
• Run DFT linting using SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Translate ATPG/MBIST patterns to tester formats (WGL/STIL) for ATE deployment.
• Support post-silicon bring-up and pattern conversion, debugging silicon failures.
• Collaborate with Product and Test Engineering to optimize test time and yield.

Skills

Verilog/SystemVerilog

DFT

ATPG

MBIST

JTAG

Scan Insertion

Scripting (Python/Tcl)

Synthesis/STA tools

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

QFocus Technologies in Sunnyvale, CA seeks a DFT Engineer to define and execute robust DFT strategies for high‑performance SoCs/ASICs. You will work with front-end design, physical design, verification, and product engineering to ensure high test coverage and streamlined post‑silicon test enablement.

Key responsibilities include implementing DFT architectures (Scan, ATPG, MBIST, IJTAG), performing scan insertion and optimization, and integrating MBIST controllers.