Senior SoC DFT Engineer - Verilog/ATPG & BIST

8613 Broadcom Corporation; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Job summary

Broadcom's ASIC Product Division in San Jose, CA is seeking an experienced ASIC DFT Engineer to join the development team. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up, test insertion, pattern generation, coverage improvements, and basic silicon debugging.

Collaboration with Physical Design and STA is essential. The ideal candidate has a strong DFT background and a track record in Verilog, ATPG/Scan, and memory BIST, with 10+ years in EE and

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field with 10+ years of experience.

Responsibilities

• Define DFT specifications for the ASIC including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration.
• Work closely with STA and DI Engineers to achieve design closure for test.
• Generate, verify and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring up.
• Assist with silicon failure analysis, diagnostics and yield improvement.
• Interface with customers, physical design and test engineering/manufacturing teams globally.
• Collaborate with IP DFT engineers and other stakeholders.
• Debug customer returned parts on the ATE.
• Innovate newer DFT solutions to solve testability problems in 3nm & beyond.
• Automate DFT & test vector generation flows.

Skills

DFT background

ATPG/Scan

Verilog

Memory BIST

Test vector generation

Scripting: TCL/Perl/Python

ATE experience

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

DFT Compiler

Mentor TestKompress

TetraMax

Fastscan

Simulation tools

Job description

Broadcom's ASIC Product Division in San Jose, CA is seeking an experienced ASIC DFT Engineer to join the development team. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up, test insertion, pattern generation, coverage improvements, and basic silicon debugging.

Collaboration with Physical Design and STA is essential. The ideal candidate has a strong DFT background and a track record in Verilog, ATPG/Scan, and memory BIST, with 10+ years in EE and