Senior ASIC DFT Engineer – SoC Test & Debug

Broadcom

San Jose (CA)

On-site

USD 144,000 - 230,000

Full time

3 days ago
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Job summary

Broadcom's ASIC Product Division seeks an ASIC DFT Engineer for our San Jose, California Development Center. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up.

The candidate will drive test insertion, pattern generation, coverage, and silicon debug while collaborating with cross-functional teams. Strong TCL/Python/C/C++ scripting and Verilog skills are expected.

Qualifications

  • Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 14+ years of experience.
  • Strong DFT and testability experience across ASIC/SoC flows.
  • Experience with scanning, BIST, ATPG and related DFT technologies.

Responsibilities

  • Define DFT specifications from customer and design requirements across ASICs.
  • Implement DFT features including Scan, MBIST, TAP, LBIST, IO, SerDes integration.
  • Collaborate with Physical Design and STA teams for design closure.
  • Generate, verify and debug Test vectors prior to tape-out.
  • Validate and debug Test vectors on ATE during silicon bring-up.
  • Assist silicon failure analysis and yield improvement efforts.
  • Interface with customers, PD and test teams globally.
  • Develop newer DFT solutions and automate flows.

Skills

DFT background
Scan insertion
ATPG vectors
Verilog coding
Memory BIST
Analog/digital design
Test automation
C++
ATE experience

Education

Electrical/Computer Engineering degree (14+ yrs)

Tools

TetraMax
Fastscan
DFT Compiler
Mentor TestKompress

Job description

Broadcom's ASIC Product Division seeks an ASIC DFT Engineer for our San Jose, California Development Center. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up.

The candidate will drive test insertion, pattern generation, coverage, and silicon debug while collaborating with cross-functional teams. Strong TCL/Python/C/C++ scripting and Verilog skills are expected.

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