Senior DFT Engineer – SoC Test, ATPG & Yield

Broadcom; San Jose (CA); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Annual discretionary bonus

Equity grants and annual equity awards

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Sick leave and vacation

Job summary

Broadcom's ASIC Product Division seeks a DFT Engineer to drive end-to-end DFT development from chip level specification to production release at the San Jose Development Center. The role involves test insertion/verification, pattern generation, coverage improvements and post-silicon debug, with collaboration across Physical Design and STA teams.

The candidate will code in TCL/Perl/Ruby/Python/C++, and work with tools like TetraMax, Fastscan, Mentor TestKompress and SB MIST to meet test metrics

Qualifications

• Strong DFT background including IO/Analog DFT, ATPG or Scan, and BIST.
• Scan insertion and compression with industry tools.
• ATPG vector generation, simulation and debugging expertise.
• Verilog coding and testbench generation.
• Memory BIST insertion and verification on embedded memory.
• Boundary scan verification with IEEE 1149.1/1149.6.
• Understanding of Test-STA and timing constraints.
• Experience with IEEE 1687/IJTAG/ICL/PDL/SSN ideals.
• Ability to work in a multi-disciplinary environment.
• Solid analog and digital circuit fundamentals.

Responsibilities

• Understand Broadcom and customer DFT feature requirements.
• Implement DFT including Scan, MBIST, TAP, LBIST, IO, and SerDes integration.
• Collaborate with STA and DI engineers for test closure.
• Generate, verify and debug test vectors before tape release.
• Validate and debug vectors on ATE during silicon bring up.
• Assist with silicon failure analysis, diagnostics and yield.
• Interface with customers and global design/test teams.
• Work with IP DFT engineers and other stakeholders.
• Debug customer returned parts on ATE.

Skills

DFT background

Scan Insertion

ATPG vector generation

Verilog coding

Memory BIST

Boundary scan

Test-STA basics

IEEE 1149.1/1149.6

Cross-discipline collaboration

Device physics fundamentals

Education

Bachelor's in Electrical/Electronic/Computer Engineering

5+ years experience or Masters with 3+ years

Tools

TCL

PERL

RUBY

PYTHON

C++

TetraMax

Fastscan

Mentor TestKompress

DFT Compiler

SSN

Job description

Broadcom's ASIC Product Division seeks a DFT Engineer to drive end-to-end DFT development from chip level specification to production release at the San Jose Development Center. The role involves test insertion/verification, pattern generation, coverage improvements and post-silicon debug, with collaboration across Physical Design and STA teams.

The candidate will code in TCL/Perl/Ruby/Python/C++, and work with tools like TetraMax, Fastscan, Mentor TestKompress and SB MIST to meet test metrics