DFT Engineering Lead for ASIC Test & Debug

Broadcom Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company match

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave

Vacation time

Job summary

Broadcom's ASIC Product Division seeks a DFT Lead for our San Jose Development Center. You will drive DFT programs from specification to implementation and verification, covering scan, MBIST, TAP, LBIST, IO, and SerDes DFT, interfacing with Physical Design and STA teams for timing closure.

Proficiency in TCL/PERL/RUBY/PYTHON/C++ is advantageous. The role involves working with cross-functional teams, external customers, and Debug/Yield improvement efforts across 7nm and beyond.

Qualifications

• Strong DFT background across IO/Analog DFT and ATPG concepts.
• Experience with scan insertion and compression tools.
• Proficient in Verilog coding, testbench creation, and simulation.
• Knowledge of Memory BIST insertion and verification for embedded memories.
• Experience with ATE validation and silicon bring-up is a plus.
• Familiarity with IEEE1149.1/1149.6 and IJTAG/PDL standards.

Responsibilities

• Define DFT specifications based on Broadcom and customer needs.
• Implement DFT features including Scan, MBIST, TAP, and IO DFT.
• Collaborate with STA and DI teams for design closure of test</br>timing.
• Generate, verify, and debug test vectors prior to tape-out.
• Validate vectors on ATE during silicon bring-up and diagnose failures.
• Interact with customers and cross-functional teams globally.

Skills

DFT background

Scan insertion

Verilog

Testbench simulation

Memory BIST

ATE experience

SerDes/PCIe

IEEE 1149

DFT Architecture

Education

Bachelor's in Electrical/Electronic/Computer Engineering

Master's in Electrical/Electronic/Computer Engineering

Tools

TetraMax

Fastscan

Job description

Broadcom's ASIC Product Division seeks a DFT Lead for our San Jose Development Center. You will drive DFT programs from specification to implementation and verification, covering scan, MBIST, TAP, LBIST, IO, and SerDes DFT, interfacing with Physical Design and STA teams for timing closure.

Proficiency in TCL/PERL/RUBY/PYTHON/C++ is advantageous. The role involves working with cross-functional teams, external customers, and Debug/Yield improvement efforts across 7nm and beyond.