DFT Engineer

Broadcom; San Jose (CA); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Annual discretionary bonus

Equity grants and annual equity awards

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Sick leave and vacation

Job summary

Broadcom's ASIC Product Division seeks a DFT Engineer to drive end-to-end DFT development from chip level specification to production release at the San Jose Development Center. The role involves test insertion/verification, pattern generation, coverage improvements and post-silicon debug, with collaboration across Physical Design and STA teams.

The candidate will code in TCL/Perl/Ruby/Python/C++, and work with tools like TetraMax, Fastscan, Mentor TestKompress and SB MIST to meet test metrics

Qualifications

• Strong DFT background including IO/Analog DFT, ATPG or Scan, and BIST.
• Scan insertion and compression with industry tools.
• ATPG vector generation, simulation and debugging expertise.
• Verilog coding and testbench generation.
• Memory BIST insertion and verification on embedded memory.
• Boundary scan verification with IEEE 1149.1/1149.6.
• Understanding of Test-STA and timing constraints.
• Experience with IEEE 1687/IJTAG/ICL/PDL/SSN ideals.
• Ability to work in a multi-disciplinary environment.
• Solid analog and digital circuit fundamentals.

Responsibilities

• Understand Broadcom and customer DFT feature requirements.
• Implement DFT including Scan, MBIST, TAP, LBIST, IO, and SerDes integration.
• Collaborate with STA and DI engineers for test closure.
• Generate, verify and debug test vectors before tape release.
• Validate and debug vectors on ATE during silicon bring up.
• Assist with silicon failure analysis, diagnostics and yield.
• Interface with customers and global design/test teams.
• Work with IP DFT engineers and other stakeholders.
• Debug customer returned parts on ATE.

Skills

DFT background

Scan Insertion

ATPG vector generation

Verilog coding

Memory BIST

Boundary scan

Test-STA basics

IEEE 1149.1/1149.6

Cross-discipline collaboration

Device physics fundamentals

Education

Bachelor's in Electrical/Electronic/Computer Engineering

5+ years experience or Masters with 3+ years

Tools

TCL

PERL

RUBY

PYTHON

C++

TetraMax

Fastscan

Mentor TestKompress

DFT Compiler

SSN

Job description

DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California Development Center. The successful candidate will work on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Responsibilities

• Understanding Broadcom & customer DFT feature requirements
• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE

Skills/Experience

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, SSN etc.)
• Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
• Basic knowledge of Test-STA and constraints
• Strong background on IEE1687, IJTAG, ICL and PDL, SSN
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug, root cause analysis and communication skills

Education & Experience

• Bachelors in Electrical/Electronic/Computer Engineering and 5+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 3+ years of relevant industry experience

Compensation And Benefits

The annual base salary range for this position is USD To USD

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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