Senior DFT Engineer - SoC Test & Bring-Up

MetAntz; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high-performance SoCs and ASICs, collaborating with front-end, physical design, verification, and product teams.

You will implement scan, ATPG, MBIST, and JTAG flows, optimize test coverage, support post-silicon bring-up, and drive test efficiency and silicon yield. Proficiency in Verilog/SystemVerilog and memory test techniques required.

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development.
• Strong HDL skills: Verilog/SystemVerilog for DFT integration and debugging.
• Experience with scan insertion, ATPG, MBIST, and JTAG.
• Memory BIST, fault models, and post-silicon support.

Responsibilities

• Define and implement DFT architectures including Scan, ATPG, MBIST and JTAG.
• Perform scan insertion, stitching, and optimization for timing closure.
• Translate pre-silicon patterns to tester formats for ATE deployment.
• Support post-silicon bring-up and yield ramp with PTE teams.

Skills

DFT Experience

Verilog

SystemVerilog

ATPG

MBIST

JTAG

Post-Silicon

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high-performance SoCs and ASICs, collaborating with front-end, physical design, verification, and product teams.

You will implement scan, ATPG, MBIST, and JTAG flows, optimize test coverage, support post-silicon bring-up, and drive test efficiency and silicon yield. Proficiency in Verilog/SystemVerilog and memory test techniques required.