Lead DFT Engineer — ASIC Test, Debug & Equity Eligible

Broadcom, Inc.; San Jose (CA); Presencial; USD 144.000 - 230.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Discretionary annual bonus

Equity grants

Medical, dental and vision plans

401(k) with company matching

Employee Stock Purchase Program

Descripción de la vacante

Broadcom, Inc. in San Jose, CA, is seeking a Principal DFT Engineer to lead DFT programs from specification to production release. You will define DFT features, implement scan and BIST, and drive test vector generation and validation on silicon.

The role requires deep experience with Verilog, ATPG, and memory BIST, close collaboration with STA/DI teams, and exposure to ATE debugging. You will interface with customers and cross-functional groups to ensure robust test coverage for 7nm and beyond.

Formación

• Bachelors in Electrical/Electronic/Computer Engineering with 12+ years of experience, or a Masters with 10+ years.
• Strong DFT background including IO/Analog DFT, ATPG, and/or Scan, BIST.
• Experience with Verilog, testbench development, and memory BIST insertion.

Responsabilidades

• Lead DFT programs from specification to production release.
• Implement DFT including Scan, MBIST, TAP, LBIST, and IO.
• Collaborate with STA, DI, and cross-functional teams.
• Validate vectors on ATE and assist silicon failure analysis.

Conocimientos

DFT

ATPG

Scan Insertion

Test Vector Gen

Verilog

Memory BIST

C++

Python

Educación

Bachelor's in Electrical/Electronic/Computer Engineering

Master's in Electrical/Electronic/Computer Engineering

Herramientas

TetraMax

Fastscan

DFT Compiler

Mentor TestKompress

Descripción del empleo

Broadcom, Inc. in San Jose, CA, is seeking a Principal DFT Engineer to lead DFT programs from specification to production release. You will define DFT features, implement scan and BIST, and drive test vector generation and validation on silicon.

The role requires deep experience with Verilog, ATPG, and memory BIST, close collaboration with STA/DI teams, and exposure to ATE debugging. You will interface with customers and cross-functional groups to ensure robust test coverage for 7nm and beyond.