Silicon Photonics Packaging Engineer (2.5D/3D)

Cisco Systems, Inc; San Jose (CA); On-site; USD 155,000 - 225,000; Full time

Job summary

Cisco Systems, Inc. seeks an Advanced Packaging engineer to join the Packaging Technology & Quality team in our Global Supply Chain.

You will drive advanced packaging technology development for silicon photonic technologies, optical engines, and co-packaged optics, collaborating with OSATs, foundries, and suppliers. You will lead design and validation of packaging test vehicles, oversee wafer processing and ultra-fine pitch interconnects, and help define DfM and DfR strategies.

Qualifications

• PhD or MS in Mechanical Engineering, Electrical Engineering, Physics, or a related field.
• 4+ years of progressive industry experience in advanced packaging with a proven track record.
• Comprehensive knowledge of advanced interconnect materials, process and assembly, including ultra-fine pitch technologies and hybrid bonding.
• Hands-on CAD experience: kLayout, APD, SolidWorks.

Responsibilities

• Develop packaging technology for silicon photonic packaging and heterogeneous integration.
• Drive definition, design and analysis of packaging test vehicles.
• Validate new technology against key performance metrics.
• Oversee wafer processing, fine pitch bumping, hybrid bonding and related assembly.
• Collaborate with foundries and partners to qualify robust packaging solutions for high density photonics.

Skills

Advanced packaging

Cross-functional collaboration

Problem solving

Technical leadership

Education

MS/PhD in Mechanical Eng/Electrical Eng/Physics

Tools

kLayout

APD

SolidWorks

Job description

Cisco Systems, Inc. seeks an Advanced Packaging engineer to join the Packaging Technology & Quality team in our Global Supply Chain.

You will drive advanced packaging technology development for silicon photonic technologies, optical engines, and co-packaged optics, collaborating with OSATs, foundries, and suppliers. You will lead design and validation of packaging test vehicles, oversee wafer processing and ultra-fine pitch interconnects, and help define DfM and DfR strategies.