Signal & Power Integrity Lead, High-Speed ASIC Packaging

Cisco Systems, Inc

San Jose (CA)

Hybrid

USD 214,000 - 310,000

Full time

9 days ago

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

Cisco Systems, Inc. is inviting a Senior Signal and Power Integrity Leader to head our ASIC packaging efforts in San Jose, CA.

You will guide a skilled SI/PI team, establish rigorous design rules for ultra-high-speed signaling, and ensure power, performance, and area targets are met across interposer, substrate, and PCB implementations. You will collaborate with layout and system partners to resolve complex SI/PI challenges, drive post-layout extraction, and mentor engineers while fostering

Qualifications

Bachelor's degree in Electrical Engineering or higher required with 10+ years in signal/power integrity.
Experience with multiple high-speed ASIC tape-outs from a package perspective.
Strong knowledge of 56G PAM4, high-speed SerDes, and channel modeling.

Responsibilities

Lead the Signal and Power Integrity Team for ASIC packaging development.
Develop and enforce design rules for ultra-high-speed signaling to meet power, performance and area goals.
Analyze substrate SI/PI and collaborate with layout for optimal interposer, substrate, and PCB solutions.
Design and document ASIC packages for high-volume release, including post-layout extraction and reporting.
Mentor junior engineers and promote design review culture across multidisciplinary teams.