Senior SI/PI Technical Leader - ASIC Packaging

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 214,000 - 310,000; Full time

Benefits offered by this job

401(k) plan with matching

Paid parental leave

Disability coverage

Health insurance

Vacation and paid time off

Job summary

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Leader in our San Jose area to guide ASIC packaging from concept through verification.

This role emphasizes ultra-high-speed signaling, SI/PI analysis, and collaboration with layout teams to optimize interposer, substrate, and PCB implementations. The position requires extensive experience with 56G PAM4, high-speed SerDes, and mature lab skills using Keysight ADS, Ansys HFSS, and Cadence APD.

Qualifications

• Bachelor's degree in Electrical Engineering or higher.
• 8+ years of signal/power integrity experience for advanced packaging.
• Experience with 56G PAM4 and high-speed SerDes architectures.
• Hands-on lab experience with SI/PI tools and layout review.

Responsibilities

• Lead SI/PI team for ASIC packaging development and verification.
• Define design rules for ultra-high-speed signaling meeting power/performance/area goals.
• Analyze substrate SI/PI and collaborate with layout for optimized solutions.
• Design ASIC packages for high-volume, high-quality releases with post-layout extraction.
• Collaborate with partners to resolve complex technical issues using advanced design rules.
• Define processes and tools for complex ASIC/package development.
• Participate in chip-architecture discussions for high-performance ASICs.

Skills

Signal integrity

Power integrity

ASIC packaging

High-speed SerDes

Team leadership

Mentoring

Education

B.S. Electrical Engineering

M.S. / Ph.D. in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS

Cadence APD

SPICE

Job description

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Leader in our San Jose area to guide ASIC packaging from concept through verification.

This role emphasizes ultra-high-speed signaling, SI/PI analysis, and collaboration with layout teams to optimize interposer, substrate, and PCB implementations. The position requires extensive experience with 56G PAM4, high-speed SerDes, and mature lab skills using Keysight ADS, Ansys HFSS, and Cadence APD.