Senior Signal & Power Integrity Lead (Remote)

Cisco; Miami (FL); À distance; USD 214 000 - 310 000; Plein temps

Résumé du poste

Cisco Silicon One is seeking a highly qualified Signal and Power Integrity Technical Leader to guide our next generation ASIC packaging. You will lead the Silicon Packaging SI/PI team to define, design, and verify packaging for Cisco platforms and collaborate with layout, system partners, and vendors.

The role emphasizes hands-on rule definition for ultra-high-speed signaling, post-layout extraction, and performance optimization, aligning power, performance, and area goals across substrates and

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of SI/PI experience, or Master's with 8+ years, or PhD with 5+ years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.

Responsabilités

• Define processes, methods, and tools for complex ASIC/package developments.
• Lead or participate in chip architecture discussions for high-performance ASICs.
• Mentor signal integrity team and influence packaging/hardware teams.
• Develop and promote design reviews, postmortems, and continuous improvement across multi-disciplined teams.
• Collaborate with system partners and vendors to resolve complex SI/PI issues.
• Lead the SI/PI team to define, design, and verify ASIC packaging for Cisco platforms.

Connaissances

Signal integrity

Power integrity

High-speed signaling

Mentor/leadership

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Outils

Keysight ADS

Ansys HFSS/EM

Cadence APD

Description du poste

Cisco Silicon One is seeking a highly qualified Signal and Power Integrity Technical Leader to guide our next generation ASIC packaging. You will lead the Silicon Packaging SI/PI team to define, design, and verify packaging for Cisco platforms and collaborate with layout, system partners, and vendors.

The role emphasizes hands-on rule definition for ultra-high-speed signaling, post-layout extraction, and performance optimization, aligning power, performance, and area goals across substrates and