Senior ASIC Packaging SI/PI Lead (Remote)

Cisco Systems, Inc.; San Jose (CA); Remote; USD 150,000 - 260,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Lead in Silicon Valley to define, design, and verify high-performance ASIC packaging for Cisco platforms.

The role focuses on ultra-high-speed signaling, SI/PI analysis, and cross-functional collaboration across layout and system teams. You will mentor junior engineers, lead design reviews, and help drive best practices in 2.5D packaging technologies, including interposer-based designs.

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of SI/PI experience or advanced degrees with fewer years.
• Expertise in high-speed design principles, transmission line theory, electromagnetics, and BER prediction.
• Proficiency in pre- and post-layout SI/PI simulations using standard EDA tools.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling with power/area goals.
• Analyze substrate SI and PI, collaborating with layout to optimize interposer, substrate, and PCB designs.
• Design, document, and develop ASIC packages for high-volume, high-quality release including post-layout extraction.

Skills

High-Speed Design & Theory

SI/PI Simulation Proficiency

Layout Review & Physical Validation

Circuit Analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Lead in Silicon Valley to define, design, and verify high-performance ASIC packaging for Cisco platforms.

The role focuses on ultra-high-speed signaling, SI/PI analysis, and cross-functional collaboration across layout and system teams. You will mentor junior engineers, lead design reviews, and help drive best practices in 2.5D packaging technologies, including interposer-based designs.