Senior ASIC Packaging SI/PI Lead - Remote-Eligible

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Benefits offered by this job

Bonus potential

Comprehensive benefits

Career growth opportunities

Job summary

Cisco Silicon One in San Jose, CA is seeking a highly experienced Signal and Power Integrity Technical Lead to help define, design and verify ASIC packaging for Cisco platforms. You will develop design rules for ultra-high-speed signaling and work with the layout team to ensure power, performance, and area goals are met.

Lead or participate in chip architecture discussions, mentor junior engineers, and drive SI/PI analyses across interposer, substrate, and PCB.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering with 8+ / 6+ / 3+ years in SI/PI.
• Experience with high-speed design principles and 56G PAM4 SerDes.
• Proficiency in pre- and post-layout SI/PI simulations using industry tools.
• Layout reviews and physical validation for signal integrity.
• SPICE-based circuit analysis and modeling experience.

Responsibilities

• Develop, document, and apply design rules for ultra-high-speed signaling.
• Analyze substrate SI/PI and collaborate with layout for optimal solutions.
• Design, document, and develop ASIC packages for high-volume releases.
• Lead or participate in chip architecture discussions for high-performance ASICs.
• Mentor SI team and influence packaging/hardware groups.
• Promote design reviews, postmortems, and continuous improvement.

Skills

High-Speed Design & Theory

SI/PI Simulation

Layout Review

Circuit Analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Silicon One in San Jose, CA is seeking a highly experienced Signal and Power Integrity Technical Lead to help define, design and verify ASIC packaging for Cisco platforms. You will develop design rules for ultra-high-speed signaling and work with the layout team to ensure power, performance, and area goals are met.

Lead or participate in chip architecture discussions, mentor junior engineers, and drive SI/PI analyses across interposer, substrate, and PCB.